Documentation
 ALTERA datasheet 
 XILINX datasheet 
 LATTICE datasheet 
 ASIC datasheet 
Application Notes Products Summary
DI2CSB

I2C Bus Interface Slave -Base version



The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can works as a slave receiver or transmitter depending on working mode determined by a master device. Very simple interface, composed with the read, write and data signals, allows easy connection to the target devices. The core does not required programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all features required by I2C specification. The DI2CSB supports the following transmission modes: Standard, Fast and High Speed.
The DI2CS is a technology independent design that can be implemented in a variety of process technologies.


Key Features

Applications

  • Conforms to v.3.0 of the I2C specification
  • Slave operation
    • Slave transmitter
    • Slave receiver
  • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies
  • Support for reads, writes, burst reads, burst writes, and repeated start
  • 7-bit addressing
  • No programming required
  • Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Low-power applications
  • Communication systems
  • Cost-effective reliable automotive systems


Symbol

 clk
 rst
 sdai
sdao 
 scli
 datai (7:0)
datao (7:0) 
rd 
wr 

Pins description

PinTypeDescription
clkinputGlobal clock
rstinputGlobal reset
sdaiinputI2C bus data line (input)
scliinputI2C bus clock line (input)
datai (7:0)inputData bus from target device
sdaooutputI2C bus data line (output)
datao (7:0)outputData bus to target device
rdoutputRead strobe for target device
wroutputWrite strobe for target device

Block diagram

Data Unit
sdai
sdao
Clock Unit
scli
Target device interface
datai (7:0)
datao (7:0)
rd
wr
Control Logic
clk
rst

Units

Data Unit

It controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.

Clock Unit

Synchronizes data and address shifts during the data transmission and reception. SCLI spikes are filtered by this unit.

Target device interface

Target device Interface performs the interface functions between DI2CSB internal blocks and target device. Allows easy connection of the core to a passive devices e.g. memory, LCD display, pressure sensors, I/O devices etc.

Control Logic

Control Logic manages execution of all commands sent via interface. Synchronizes internal data flow.

Performance


Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

ImplementationSpeed
grade
Utilized Area
[LC]
Frequency
[MHz]
APEX20KC-795170
STRATIX-595230
CYCLONE-695195

DI2CSB implementation results for ALTERA devices. The all features have been included.

ImplementationSpeed
grade
Utilized Area
[LUT/PFU]
Frequency
[MHz]
XP-5118/27180
ECP-5118/27212
EC-5118/27203
ECP2-778/42317
ECP2M-770/27318
SC-776/42323
XP2-770/27263

DI2CSB implementation results for LATTICE devices. The all features have been included.

ImplementationSpeed
grade
Utilized Area
[Slices]
Frequency
[MHz]
SPARTAN-IIE-743178
SPARTAN-3-543217
SPARTAN-3E-443153
VIRTEX-E-845185
VIRTEX-II-643336
VIRTEX-II pro-743382
VIRTEX-4-1243392

DI2CSB implementation results for XILINX devices. The all features have been included.


Family summary

DesignI2C specificationOperation typeStandard mode   Fast     modeFast Plus modeHigh Speed modeMulti master7 bit address10 bit addressInterrupt gen.Passive elements interfaceMicrocontroller interfaceUser defined timing
100 kb/s400 kb/s1 Mb/s3.4 Mb/s
DI2CMv. 3.0MASTER++++++++-++
DI2CSv. 3.0SLAVE++++++-+-++
DI2CSBv. 3.0SLAVE++++++--+--
DI2CMSv. 3.0MASTER/SLAVE++++++++-++


The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application.