8-bit RISC Microcontroller

The DFPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, dedicated for operation with fast memory. The core has been designed with a special concern about low power consumption assuring the best power consumption and performance combination.
The DFPIC1655X is a software compatible with the industry standard PIC 16XXX Microcontrollers.... It employs a modified RISC architecture (2 times faster than original implementation).
The DFPIC1655X have enhanced core features, configurable hardware stack, and multiple internal and external interrupt sources. The separate instruction and data buses allow a 14 bit wide instruction word with the separate 8-bit wide data. The DFPIC1655X typically achieve a 2:1 code compression and a 8:1 speed improvement over other 8-bit microcontrollers in their class.
The power-down mode SLEEP allow user to significanlty reduce power consumption, and "wake up" the controller through several external and internal interrupts and resets. An integrated Watchdog Timer with it's own dedicated clock signal provides protection against software lock-up.
The DFPIC1655X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices make this IP core perfect for applications with space and power consumption limitations.
DFPIC1655X is delivered with fully automated testbench, complete set of tests and hardware on-chip debugger DoCD^TM allowing easy package validation at each stage of SoC design flow.


Each of the DCD's PIC Core has built in support for DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

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Software compatible with industry standard PIC16C55X Harvard RISC architecture 2 times faster compared to original implementation 35 instructions 14 bit wide instruction word Up to 32 kB of internal Data Memory Up to 64K bytes of Program Memory Configurable hardware stack Power saving SLEEP mode Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready Technology independent HDL Source Code The following parameters of the DFPIC1655X core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. Data Memory size up to 32kB default 512 Bytes Program Memory size up to 64k Words default 8k Number of hardware stack levels 1-16 default 4 SLEEP mode used unused WDT Timer used/ width unused Timer 0 used unused Interrupt controller used unused Ports A,B used unused DoCDTM debug unit used unused Besides mentioned above parameters all available peripherals can be excluded from the core by changing appropriate constants in package file.

DoCDTMDebugger Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface Two 8 bit I/O ports Two 8-bit corresponding TRIS registers Interrupt feature on PORTB(7:4) change Timer 0 8-bit timer/counter Readable and Writable 8-bit software programmable prescaler Internal or external clock select Interrupt generation on timer overflow Edge select for external clock Watchdog Timer Configurable Time out period 7-bit software programmable prescaler Dedicated independent Watchdog Clock input Interrupt Controller Three individually maskable Interrupt sources External interrupt INT Timer Overflow interrupt Port B[7:4] change interrupt

Pin	Type	Description
clk	input	Global clock
por	input	Global reset Power On Reset
mclr	input	User reset
prgdata (13:0)	input	Data bus from program memory
portai (7:0)	input	Port A input
portbi (7:0)	input	Port B input
int	input	External interrupt
ramdatai (7:0)	input	Data bus from int. data memory
t0cki	input	Timer 0 input
clkwdt	input	Watchdog clock
docddatai	input	DoCDTM data input
sleep	output	Sleep signal
prgaddr (15:0)	output	Program memory address bus
portao (7:0)	output	Port A output
portbo (7:0)	output	Port B output
trisa (7:0)	output	Data direction pins for Port A
trisb (7:0)	output	Data direction pins for Port B
ramdatao (7:0)	output	Data bus for internal data memory
ramaddr (8:0)	output	RAM address bus
ramwe	output	Data memory write
ramoe	output	Data memory output enable
docddatao	output	DoCDTM data output
docdclk	output	DoCDTM clock line
prgdatao (13:0)	output	Program memory data bus output
prgwe	output	Program memory write enable