Configurable UART with FIFO

The D16550 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. The D16550 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The D16550 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (2¹⁶-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16550 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
The D16550 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The D16550 is a technology independent design that can be implemented in a variety of process technologies.

The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.
The configuration capability allow user to enable or disable during Synthesis process the Modem Control Logic and FIFO's or change the FIFO's size. So in applications with area limitation and where the UART works only in 16450 mode, disabling of Modem Control and FIFO's allow to save about 50% of logic resources.
The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16550 core implementation and verification are very simply, by eliminating a number of clock trees in complete system.

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Software compatible with 16450 and 16550 UARTs Configuration capability Separate configurable BAUD clock linee Majority Voting Logic Supports RS232 and RS485 standards Two modes of operation: UART mode and FIFO mode In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data Independently controlled transmit, receive, line status, and data set interrupts False start bit detection 16 bit programmable baud generator Independent receiver clock input MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD) Fully programmable serial-interface characteristics: 5-, 6-, 7-, or 8-bit characters Even, odd, or no-parity bit generation and detection 1-, 1½-, or 2-stop bit generation Internal baud generator Complete status reporting capabilities Line break generation and detection. Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Break, parity, overrun, framing error simula-tion Full prioritized interrupt system controls Available system interface wrappers: AMBA - APB Bus Altera Avalon Bus Xilinx OPB Bus Fully synthesizable Static synchronous design and no internal tri-states		Serial Data communications applications Modem interface Embedded microprocessor boards The following parameters of the D16550 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. Baud generator enable disable External RCLK source enable disable External BAUDCLK source enable disable Asynchronous input buffer enable disable Modem Control enable disable SCR register enable disable FIFO Control logic enable disable FIFO's size 2 4 8 16 - default

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
rclk	input	Receiver clock
si	input	Serial data input
cts	input	Clear to send input
dsr	input	Data set ready input
dcd	input	Data carrier detect input
ri	input	Ring indicator input
datai (7:0)	input	Parallel data input
rd	input	Read input
wr	input	Write input
cs	input	Chip select
addr (2:0)	input	Address bus
baudclken	input	Baud generator clock enable
baudclk	input	Baud generator clock
so	output	Serial data output
temt	output	Transmitter Empty - used to control RS485 buffer
rts	output	Request to send output
dtr	output	Data terminal ready output
out1	output	Output 1
out2	output	Output 2
intr	output	Interrupt request output
datao (7:0)	output	Parallel data output
ddis	output	Driver disable output
txrdy	output	Transmitter ready output
rxrdy	output	Receiver ready output
baudout	output	Baud generator output