8-bit Microcontroller

The D68HC08 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. The D68HC08 soft core is binary and cycle - compatible with the industry standard Motorola 68HC08 8-bit microcontroller. The Core in standard configuration has integrated on chip major peripheral functions.
The D68HC08 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI), and the Synchronous Serial Peripheral Interface (SPI).
Two 16-bit, flexible timing systems with input capture lines, output-compare lines and PWM functionality
Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the D68HC08 IP Core especially attractive for automotive and battery-driven applications.
D68HC08 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


Each DCD's D68XX Core has built in support for DCD Hardware Debug System called DoCD^TM. It's a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

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Standard architecture, cycle compatible with original implementation Software compatible with industry standard 68HC08 Up to 64K bytes of Data Memory Up to 64K bytes of Code Memory De-multiplexed Address/Data Bus to allow easy memory connection Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories. Fully synthesizable Static synchronous design No internal reset generator or gated clock Positive edge clocking and no internal tri-states Scan test ready One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use Synchronous logic without microcode The D68HC08 Microcontroller Core has built in hardware on chip debugger DoCDTM which can be easily switched on/of by changing single parameter in the core package. This configurability allows user to have the DoCD "on board" at the prototyping level, and then switch it off in mass production. This feature allows to save space in silicon in production items. DoCDTM debug unit used unused Also peripheral components are configurable the same way as DoCD. Besides mentioned above parameter all available peripherals can be excluded from the core by changing appropriate constants in package file.

DoCDTM debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface Eight I/O Ports Extended Interrupt Controller 16-bit Timer Interface Modules TIMA and TIMB Four input capture/compare channels Buffered and unbuffered PWM Programmable TIM clock input Free-running or modulo up-count operation TIM counter stop and reset bits Programmable Interrupt Timer (PIT) Programmable PIT clock input Free-running or modulo up-count operation PIT counter stop and reset bits Full-duplex UART - SCI Standard Non-return to Zero format (NRZ) 8 or 9 bit data transfer Integrated BAUD Rate generator Enhanced receiver data sampling technique Noise, Overrun and Framing errors detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE Three SCI Related interrupts SPI – Master and Slave Serial Peripheral Interface Supports speeds up ¼ of system clock Mode fault error Write collision error Software selectable polarity and phase of serial clock SCK System errors detection Allows operation from a wide range of system clock frequencies Interrupt generation

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
cmf	input	Clock monitor fail reset
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
irq	input	External Interrupt Request
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line
porta (7:0)	output	Port A - general-purpose bidirectional I/O Port.
portb (7:0)	output	Port B is a special function port, that in original uC shares all of its port pins with ADC module.
portc (7:0)	output	Genaral-purpose bidirections I/O Port.
portd (7:0)	output	Port D is a special function port, which shares two it's pins with the timer interface module.
porte (7:0)	output	Port E is a special function bidirectional I/O port,shared with Serial Peripheral Interface (SPI), Timer A (TIMA) a,d Serial Communication Interface (SCI).
portf (7:0)	output	Port F - General purpose bidirectional I./O Port, shared with Timer A and Timer B.
halt	output	Halt clock system during STOP Instruction