Digital Core Design

The Power of Intellectual Property

HAD2 Kit - debugger

The HAD2 Kit is an integral part of DoCDTM Hardware Debuger System. The HAD2 is a high-performance Hardware Assisted Debugger, connected to the target system containing the DCD's DQ8051/DQ80251/DP8051/DXPIC16XXX/DF68XX Microcontroller Core, either in FPGA or ASIC. HAD2 is a small hardware adapter, that manages communication between the Debug IP Core (TTAG/JTAG/DTAG protocol) inside the silicon and a USB port of the host PC, running DoCDTM Debug Software.

The HAD2 Kit contains:

HAD2 Features

  • USB communication interface to target host at FULL speed
  • Synchronous communication interface to Debug IP Core
    • TTAG two-wire interface - Debug IP v4.70
    • JTAG interface - Debug IP v4.00 and above
    • DTAG three-wire interface - Debug IP v3.xx
  • I/O voltages signalized by diode
    • 3.3 Volt systems
    • 2.5 Volt syatems
    • 1.8 Volt systems
    • 1.5 Volt systems
  • Single power supply directly from USB
  • Small physical dimensions

DoCD Debug IP Core

  • Processor execution control
    • Run, Halt
    • Reset
    • Step into instruction
    • Skip instruction
  • Read-write all processor contents
    • Program Counter (PC)
    • Program Memory
    • Internal (direct) Data Memory
    • Special Function Registers (SFRs)
    • External Data Memory
  • Code execution breakpoints
    • two real-time PC breakpoint
    • unlimited number of real-time OPCODE breakpoints (v 4.00 and above)
  • Hardware execution watch-points
    • two at Internal (direct) Data Memory
    • two at Special Function Registers (SFRs)
    • two at External Data Memory
  • Hardware watch-points activated at a
    • certain address by any write into memory
    • certain address by any read from memory
    • certain address by write into memory a required data
    • certain address by read from memory a required data
  • Unlimited number of software watch-points
    • Internal (direct) Data Memory
    • Special Function Registers (SFRs)
    • External Data Memory
  • Unlimited number of software breakpoints
    • Program Memory
  • Automatic adjustment of debug data transfer speed rate between HAD2 and Silicon
  • Communication interface
    • TTAG two-wire interface - Debug IP v4.70
    • JTAG interface - v4.00 and above
    • DTAG three-wire communication - v3.xx
  • Fully static synchronous design with no internal tri-states

DoCD Debug Software

  • In-system FLASH programming
  • Three working modes
    • hardware debugger
    • In Circuit Emulator - ICE
    • software simulator
  • Source Level Debugging:
    • C level hardware/software breakpoints
    • C code execution
      • line by line
      • over line
      • out of function
      • skip line
    • ASM code execution
      • instruction by instruction
      • over instruction
      • out of function
      • skip instruction
    • ASM, C source view of code
  • Symbol Explorer provides hierarchical tree view of all symbols:
    • modules
    • functions
    • blocks
    • variables and more
  • Contents sensitive Watch window
  • Symbolic debug including:
    • code
    • variables
    • variable types
  • Unlimited number of Real-time hardware breakpoints
    • Program Memory (CODE)
  • Two real-time hardware watch-points for each space:
    • Internal (direct) Data Memory (IDM)
    • Special Function Registers (SFR)
    • eXternal Data Memory (XDM)
  • Unlimited number of software breakpoints
    • Program Memory
    • Internal (direct) Data Memory (IDM)
    • Special Function Registers (SFR)
    • eXternal Data Memory (XDM)
  • Set/clear software or hardware breakpoints, watch-points in Disassembled and C Source Code windows
  • 1024 steps deep Software Trace
  • Load Program Memory content from:
    • OMF-51, extended OMF-51 files
    • OMF-251 file
    • Intel HEX-51, HEX-386 files
    • BIN file
  • Auto refresh of all windows during execution of program
    • Registers panel including ACC, B, PSW, PC, SP, DPTR, DPP and four banks of general purpose registers R0-R7
    • Internal (direct) Data Memory (IDM)
    • Special Function Registers (SFR)
    • eXternal Data Memory (XDM)
    • Timers/Counters
    • UARTs
    • I/O Ports
  • Dedicated windows for peripherals
  • Configurable auto refresh time period with 1s step resolution
  • Status bar containing number of actually executed instructions, number of clock periods and real processor speed rate
  • Hardware Assisted Debugger interface
    • TTAG interface
    • JTAG interface
    • DTAG interface
  • The system runs on a Windows 2000/XP/Vista/7.8/8.1 (both 32 and 64 bit) PC
  • Supports software tools from Keil, Archimedes, IAR, Tasking, Franklin, SDCC and the others

DoCD System Features Description


All FLASH memory devices are supported by DoCD debug system. Such support is assured by configurability of FLASH programming algorithm and supported devices database. New FLASH device can be easily added to existing base, by using built-in editor. DoCD debugger allows user to simply perform in-system programming of its FLASH memory, without using any additional equipment. DoCD programming task is performed directly within Debug software and after uploading the code, it is ready for debugging. Programming time is very short and write operations are performed with maximum allowed speed, by certain FLASH device.


The number of hardware breakpoints is unlimited. Like software breakpoints, hardware execution breakpoints can be set in Program Memory space. They stop program execution just prior an instruction pointed by Program Counter (PC). In other words, instruction located at the PC breakpoint address is not executed. The difference is found in the method of program execution. In this case, program is running with full clock speed (in real-time) and processor is halted, when hardware signalizes true breakpoint condition.


The number of hardware watch-points is limited to six in different address spaces. Like software breakpoints, hardware execution watch-points can be set in direct RAM, SFRs and external RAM. They stop program execution after an instruction being executed. The difference is found in the method of program execution. In this case program is run with full clock speed (in real-time), and processor is halted when hardware signalizes true watch-point condition.


An unlimited number of software breakpoints can be set anywhere in the physical address space of the processor. It means, that the breakpoints can be set in Program Memory space, direct RAM, SFRs and external RAM. If at least one software breakpoint is set, program is executed in automatic step by step mode, with checking, if certain breakpoint condition is met. Program execution is halted when breakpoint condition is already met, and its execution can be resumed at any time, in any appropriate mode.


Mixed breakpoint mode is also allowed and it means that software and hardware breakpoints and watch-points are mixed in the system. That gives the user flexibility in the debugging. For example, two different break conditions can be set, using watch-points and hardware breakpoints. In each breakpoint mode halt means: CPU is halted and instructions are no longer being fetched and all internal peripherals are also stopped (e.g. timers, watchdog). The UARTs work correctly in any case.


Symbol Explorer provides hierarchical tree view of all C project symbols. It supports all C types, variables, constants, functions, and symbolic names of registers. Along with watch window, it provides flexible and powerful debugging feature, at high C language level.


Because many SoC designs have both power and gate limitations, DCD provides a scaled solution. Debug extensions can be scaled to control gate counts. The benefits are fewer gates, lower power and core size, while trading off debug capability.


A Pentium class computer, with minimum 32 MB of memory, 10 MB of free space on Hard Disk, CD-ROM drive, USB port and Windows 2000/XP/Vista/7/8/8.1 (both 32 and 64 bit) operating system, are required.